DS506 Datasheet, PDF (3/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Functional Description
The Endpoint cores for PCI Express are organized into four main modules based on the three discrete
logical layers defined by the PCI Express Base Specification. The four logic modules, which manage all
the system-level functions, include the following:
• Physical Layer Module (PLM)
• Data Link Layer Module (LLM)
• Transaction Layer Module (TLM)
• Configuration Management Module (CMM)
Each module is further partitioned into the Receive and the Transmit sections. The Receive section pro-
cesses the inbound information, and the Transmit section processes the outbound information. Figure 1
illustrates the main modules interfacing with one another and the user application using the following
set of four interfaces:
• System interface (SYS)
• PCI Express interface (PCI EXP)
• Configuration interface (CFG)
• Transaction interface (TRN)
X-Ref Target - Figure 1
Endpoint for PCI Express
User
Logic
Transaction
(TRN)
Transaction
Layer
Data Link
Layer
Physical
Layer
PCI Express
(PCI_EXP)
PCI
Express
Fabric
Host
Interface
Configuration
(CFG)
Configuration Management Layer
System
(SYS)
Clock
and
Reset
Figure 1: Endpoint Top-level Functional Blocks and Interfaces
The core allows the use of packets to exchange information between modules. Packets are formed in the
Transaction and Data Link Layers to carry information from the transmitting component to the receiv-
ing component. Necessary information is added to the packet being transmitted, which is required to
handle the packet at specific layers. At the receiving end, each layer of the receiving element processes
the incoming packet, strips the relevant information and forwards the packet to the next layer. As a
result, the received packets are transformed from their Physical Layer representation to their Data Link
Layer representation and Transaction Layer representation.
The primary logic modules comprising the Endpoint core for PCI Express and their interfaces are
described in the sections that follow.
DS506 April 19, 2010
www.xilinx.com
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Product Specification