DS506 Datasheet, PDF (2/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Features
• High-performance, highly flexible, scalable, and reliable, general purpose I/O solution
♦ Compliant with the PCI Express Base Specification v1.1
♦ Compatible with conventional PCI software model
• Incorporates Xilinx Smart-IP™ technology to guarantee critical timing
• Uses embedded RocketIO™ transceivers to achieve high-transceiver capability
♦ 2.5 Gbps line speed
♦ Supports 1-lane, 4-lane, and 8-lane operation
♦ Elastic buffers and clock compensation
♦ Automatic clock data recovery
• 8B/10B encode and decode
• Offers standardized user interface
♦ Easy-to-use packet-based protocol
♦ Full-duplex communication
♦ Back-to-back transactions enable greater link bandwidth utilization
♦ Supports flow control of data and discontinuation of an in-process transaction in transmit
direction
♦ Supports flow control of data in receive direction
♦ Support for automatic handling of error forwarded packets
• Supports removal of corrupted packets for error detection and recovery
• Compliant with PCI/PCI-Express power management functions
• Supports a maximum transaction payload of up to 512 bytes
• Bandwidth scalability with frequency and/or interconnect width
• Fully compliant with PCI Express transaction ordering rules
• Design verified using a Xilinx proprietary test bench
Applications
The Endpoint for PCI Express core architecture enables a broad range of computing and communica-
tions target applications, emphasizing performance, cost, scalability, feature extensibility and mission-
critical reliability. Typical applications include
• Data communications networks
• Telecommunications networks
• Broadband wired and wireless applications
• Cross-connects
• Network interface cards
• Chip-to-chip and backplane interconnect
• Crossbar switches
• Wireless base stations
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www.xilinx.com
DS506 April 19, 2010
Product Specification