DS506 Datasheet, PDF (8/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Table 4: PCI Express Interface Signals for the 4-lane Endpoint Core
Lane
Number
Name
Direction
Description
0
pci_exp_txp0
Output PCI Express Transmit Positive: Serial Differential Output 0 (+)
0
pci_exp_txn0
Output PCI Express Transmit Negative: Serial Differential Output 0 (–)
0
pci_exp_rxp0
Input PCI Express Receive Positive: Serial Differential Input 0 (+)
0
pci_exp_rxn0
Input PCI Express Receive Negative: Serial Differential Input 0 (–)
1
pci_exp_txp1
Output PCI Express Transmit Positive: Serial Differential Output 1 (+)
1
pci_exp_txn1
Output PCI Express Transmit Negative: Serial Differential Output 1 (–)
1
pci_exp_rxp1
Input PCI Express Receive Positive: Serial Differential Input 1 (+)
1
pci_exp_rxn1
Input PCI Express Receive Negative: Serial Differential Input 1 (–)
2
pci_exp_txp2
Output PCI Express Transmit Positive: Serial Differential Output 2 (+)
2
pci_exp_txn2
Output PCI Express Transmit Negative: Serial Differential Output 2 (–)
2
pci_exp_rxp2
Input PCI Express Receive Positive: Serial Differential Input 2 (+)
2
pci_exp_rxn2
Input PCI Express Receive Negative: Serial Differential Input 2 (–)
3
pci_exp_txp3
Output PCI Express Transmit Positive: Serial Differential Output 3 (+)
3
pci_exp_txn3
Output PCI Express Transmit Negative: Serial Differential Output 3 (–)
3
pci_exp_rxp3
Input PCI Express Receive Positive: Serial Differential Input 3 (+)
3
pci_exp_rxn3
Input PCI Express Receive Negative: Serial Differential Input 3 (–)
8
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DS506 April 19, 2010
Product Specification