DS506 Datasheet, PDF (15/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Table 8: Transmit Path Clock Cycle Signals
Clock Cycle
Event Description
7
Frame B QWORD D1 is transferred. The trn_trem_n[7:0] bus specifies the valid bytes on the
last QWORD.
Note that trn_tdst_rdy_n is not deasserted to offer the user application the option to start the
8
transmission of the next TLP, even though it can be stalled before being completed until a buffer
becomes available.
Receive TRN Interface
Table 9 defines the receive (Rx) TRN interface signals.
Table 9: Receive Transaction Interface Signals
Name
Direction
Description
trn_rsof_n
Output
Receive Start-of-Frame (SOF): Signals the start of a packet. Active
low.
trn_reof_n
Output Receive End-of-Frame (EOF): Signals the end of a packet. Active low.
trn_rd[W-1:0]
Output
Receive Data: Packet data being received.
Product Name
Data Bus Width (W)
1-lane 64-bit Endpoint
64
4-lane 64-bit Endpoint
64
8-lane 64-bit Endpoint
64
1-lane 32-bit Endpoint
32
4-lane 32-bit Endpoint
32
trn_rrem_n[7:0]⁽¹⁾
Output
Receive Data Remainder: Valid only if both trn_reof_n and
trn_rdst_rdy_n are asserted. Legal values are:
0000_0000b = packet data on all of trn_rd[63:0],
0000_1111b = packet data only on trn_rd[63:32]
trn_rerrfwd_n
Output
Receive Error Forward: Marks the current packet in progress as error-
poisoned. Asserted by the core at EOF. Active low.
trn_rsrc_rdy_n
Output
Receive Source Ready: Indicates that the core is presenting valid
data on trn_rd[W-1:0]. Active low.
trn_rdst_rdy_n
Input
Receive Destination Ready: Indicates that the user application is
ready to accept data on trn_rd[W1:0]. Active low. Simultaneous
assertion of trn_rsrc_rdy_n and trn_rdst_rdy_n marks the successful
transfer of data on trn_rd[W-1:0].
trn_rsrc_dsc_n
Output
Receive Source Discontinue: Indicates that the core is aborting the
current packet transfer. Asserted when the physical link is going into
reset. Active low.
trn_rnp_ok_n
Input
Receive Non-Posted OK: The user application asserts this whenever
it is ready to accept a Non-Posted Request packet. This allows Posted
and Completion packets to bypass Non-Posted packets in the inbound
queue if necessitated by the user application. Active low.
When the user application approaches a state where it is unable to
service Non-Posted Requests, it must deassert trn_rnp_ok_n one
clock cycle before the core presents EOF of the last Non-Posted TLP
the user application can accept.
DS506 April 19, 2010
www.xilinx.com
15
Product Specification