DS506 Datasheet, PDF (5/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
support for PME event generation. Also implemented are user-triggered error message generation and
user-read access to the device configuration space.
PCI Configuration Space
The PCI Configuration Space block provides a standard Type 0 configuration space, consisting of a 64-
byte, Type 0 configuration space header with an additional 192 bytes used for extended capabilities.
Four extended capabilities are provided in the interface:
• Express capability structure
• Power management capability structure
• Message signaled interrupt capability structure
• Device serial number extended capability structure
These capabilities, together with the standard Type 0 header shown in Table 1, support software driven
Plug and Play initialization and configuration.
DS506 April 19, 2010
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Product Specification