DS506 Datasheet, PDF (7/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Endpoint Interfaces
The Endpoint core includes top-level signal interfaces that have sub-groups for the receive direction,
transmit direction, and the signals common to both directions.
System Interface
Table 2 defines the System (SYS) interface signals. The system reset (sys_reset_n) signal is an asyn-
chronous input (active low). The assertion of this signal causes a hard reset of the entire endpoint,
including the Rocket IO transceiver. In the CEM add-in card form factor, the PERST# signal should be
connected to the sys_reset_n signal. For form factors where no sideband reset is available, it must be
generated locally.
The system clock signal (sys_clk) is used to clock the entire endpoint, including the Rocket IO trans-
ceiver. The system clock is used to clock logic that coordinates the hardware reset process. This clock
must be a free-running clock that is not a DCM output. See the “Digital Design Considerations” chapter
of the Rocket I/O Transceiver User Guide for more information. Additional information about core clock-
ing consideration can be found in Answer Record 20600.
Table 2: System Interface Signals
Name
Direction
Description
sys_reset_n
Input
System Reset: An asynchronous input (active low) signal reset from the root
complex/system that puts the endpoint in a known initial state.
sys_clk
Input
Reference Clock: The reference clock for the PCI Express Endpoint
solutions.
Product
Virtex-4
Virtex-5
1-lane 64-bit Endpoint
250 MHz
N/A
4-lane 64-bit Endpoint
250 MHz
N/A
8-lane 32-bit Endpoint
250 MHz
100 MHz
1-lane 32-bit Endpoint
250 MHz
100 MHz
4-lane 32-bit Endpoint
250 MHz
100 MHz
PCI Express Interface
The PCI Express (PCI_EXP) interface consists of differential transmit and receive pairs organized in
multiple lanes. A PCI Express lane consists of a pair of transmit differential signals (pci_exp_txp,
pci_exp_txn) and a pair of receive differential signals (pci_exp_rxp, pci_exp_rxn). The 1-lane
core supports only lane 0, while the 4-lane core supports lanes 0-3, and the 8-lane core support lanes 0-
7. Table 3 and Table 4 define the transmit and receive signals of the PCI_EXP interface signals for 1- and
4-lane cores, respectively. Table 5 describes the signals for the 8-lane core.
Table 3: PCI Express Interface Signals for the 1-lane Endpoint Core
Lane
Number
Name
Direction
Description
0
pci_exp_txp0
Output
PCI Express Transmit Positive: Serial Differential Output 0 (+)
0
pci_exp_txn0
Output
PCI Express Transmit Negative: Serial Differential Output 0 (–)
0
pci_exp_rxp0
Input
PCI Express Receive Positive: Serial Differential Input 0 (+)
0
pci_exp_rxn0
Input
PCI Express Receive Negative: Serial Differential Input 0 (–)
DS506 April 19, 2010
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Product Specification