DS506 Datasheet, PDF (14/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Table 7: Transmit Transaction Interface Signals (Cont’d)
Name
Direction
Description
trn_tdst_dsc_n
Output
Transmit Destination Discontinue: Indicates that the core is aborting the
current packet. Asserted when the physical link is going into reset. Active
low.
trn_tbuf_av [N-1:0]
Output
Transmit Buffers Available: Number of transmit buffers available in the
core. The maximum number is 32. Each transmit buffer can accommodate
one TLP up to the supported Max_Payload_Size.
Product Name
Tx Buffers Available Width (N)
1-lane 64-bit Endpoint
16
5
4-lane 64-bit Endpoint
16
5
8-lane 64-bit Endpoint
32
6
1-lane 32-bit Endpoint
8
5
4-lane 32-bit Endpoint
16
5
1. trn_trem[7:0] is not supported or necessary for the 1-lane and 4-lane 32-bit endpoint products.
Figure 2 illustrates the transfer on the TRN interface of two TLPs to be transmitted on the PCI Express
Link. Every valid transfer can be up to a Quad Word (QWORD) of data.
X-Ref Target - Figure 2
trn_tch[2:0]
0
0
trn_tsrc_rdy_n
trn_td[63:0]
A-D0 A-D1 A-D2 A-D3 B-D0 B-D1
trn_tsof_n
trn_teof_n
trn_trem_n[7:0]
00
0F
Figure 2: Tx TRN Interface (64-bit Transaction Interface shown)
Table 8 defines and describes the transmit path clock cycle signals.
Table 8: Transmit Path Clock Cycle Signals
Clock Cycle
Event Description
1
The Endpoint core for PCI Express signals that it can accept the transfer of a TLP, with the
assertion of trn_tdst_rdy_n.
2
The user application initiates the transfer with the assertion of trn_tsrc_rdy_n and trn_tsof_n.
The combined assertion of trn_tsrc_rdy_n and trn_tdst_rdy_n marks a data transfer.
3
Frame A QWORD D1 is transferred.
4
Frame A QWORD D2 is transferred.
5
The trn_trem_n[7:0] bus specifies the valid bytes on the last QWORD.
6
Frame B QWORD D0 is transferred.
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DS506 April 19, 2010
Product Specification