DS506 Datasheet, PDF (1/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

DS506 April 19, 2010
LogiCORE IP Endpoint v3.7
for PCI Express^®
Product Specification
Introduction
The LogiCORE™ Endpoint for PCI Express® offers
high-bandwidth, scalable, and reliable serial intercon-
nect intellectual property building blocks for use with
Virtex®-4, and Virtex-5 devices. All cores in the solu-
tion (1-lane, 4-lane, and 8-lane) are protocol-compliant
and electrically compatible with the PCI Express Base
Specification v1.1.
PCI Express (PCIe®) offers a serial architecture that
alleviates some of the limitations of parallel bus archi-
tectures by using clock data recovery (CDR) and differ-
ential signaling. Using CDR (as opposed to source
synchronous clocking) lowers pin count, enables supe-
rior frequency scalability, and makes data synchroniza-
tion easier. The layered architecture of PCIe provides
for future attachment to copper, optical, or emerging
physical signaling media. PCIe technology, adopted by
PCI-SIG as the next generation PCI, is backward-com-
patible to the existing PCI software model.
With higher bandwidth per pin, low overhead, low
latency, reduced signal integrity issues, and CDR archi-
tecture, the Xilinx Endpoint solution for PCI Express
sets the industry standard for a high-performance, cost-
efficient third-generation I/O solution.
The Xilinx Endpoint solution for PCIe is compatible
with industry-standard application form factors such
as the PCI Express Card Electromechanical (CEM) v1.1
and the PCI Industrial Computer Manufacturers Group
(PICMG) 3.4 specifications.
The Endpoint solutions for PCIe are defined in the fol-
lowing table.
Product
1-lane 64-bit Endpoint
4-lane 64-bit Endpoint
8-lane 64-bit Endpoint
1-lane 32-bit Endpoint
4-lane 32-bit Endpoint
FPGA Support
Data Path
Width
Virtex-4 FX
64
Virtex-4 FX
64
Virtex-5 LX, Virtex-4 FX
64
Virtex-5 LX, Virtex-4 FX
32
Virtex-5 LX, Virtex-4 FX
32
LogiCORE Facts
Core Specifics
Device
Families ⁽¹⁾
Virtex-4 FX⁽²⁾, Virtex-5 LX^(2),(3)
Minimum
Device
Require-
ment
1-lane 64-bit Endpoint
4-lane 64-bit Endpoint
8-lane 64-bit Endpoint
1-lane 32-bit Endpoint
4-lane 32-bit Endpoint
Endpoint (EP) Product
1-lane 64-bit Endpoint
XC4VFX20 -10
XC4VFX20 -10
XC4VFX60 -11/XC5VLX50T-1
XC4VFX20 -10/XC5VLX50T-1
XC4VFX20 -11/XC5VLX50T-1
I/O ⁽⁴⁾
1 ⁽⁵⁾
LUT
7800
FF
7000
4-lane 64-bit Endpoint
4
10550
9200
8-lane 64-bit EP Virtex-4
8-lane 64-bit EP Virtex-5
8
13500
11400
12000
11200
1-lane 32-bit EP Virtex-4
1-lane 32-bit EP Virtex-5
1 ⁽⁵⁾
6300
5100
5100
4700
Resources
Used
4-lane 32-bit EP Virtex-4
4-lane 32-bit EP Virtex-5
4
Block
RAM
8700
7200
CMPS ⁽⁶⁾
# Tx
Buffers
7000
6700
CMPS
1-lane 64-bit Endpoint
12
16
512
4-lane 64-bit Endpoint
12
16
512
8-lane 64-bit EP Virtex-4
12
8-lane 64-bit EP Virtex-5
6
32
256
1-lane 32-bit EP Virtex-4
8
1-lane 32-bit EP Virtex-5
4
8
512
4-lane 32-bit EP Virtex-4
4-lane 32-bit EP Virtex-5
Special Features
12
6
16
512
Rocket IO™ Transceivers⁽⁴⁾,
Digital Clock Manager, block RAM
Provided with Core
Documentation
Product Specification, Getting Started Guide
User Guide, Instantiation Template
Design Files
Verilog® and VHDL Simulation Models
Xilinx Generic Netlist Format (ngo netlist)
Verilog Example Test Bench & Example Design
Constraints File
User Constraints File (UCF)
Design Tool Support
HDL Synthesis Tool
Synplicity® Synplify®, Xilinx XST
Implementation Tools
Xilinx ISE® v12.1
Verification Tools
(SWIFT-compliant
simulator required)
Cadence™ Incisive Enterprise Simulator (IES) v9.2
and above,
Synopsys® VCS and VCS MX 2009.12 and above
, Mentor Graphics® ModelSim® v6.5c and above
Support
Provided by Xilinx, Inc. @ www.xilinx.com/support
1. For the complete list of supported devices, see the 12.1 release notes for this
core.
2. Virtex-4 and Virtex-5 solutions require the latest production silicon stepping
and are pending hardware validation. The Xilinx LogiCORE warranty does
not include production usage with engineering sample silicon (ES).
3. XC5VLX50T, XC5VLX110T, and XC5VLX330T are supported.
4. RocketIO Multi-Gigabit Transceiver (MGT) for Virtex-4, RocketIO GTP
Transceiver for Virtex-5.
5. In Virtex-4 and Virtex-5 devices, the 1-lane Endpoint core consumes an en-
tire RocketIO transceiver pair. One RocketIO transceiver tile is used for lane
0; the other is unused and tied off inside the core.
6. CMPS: Capability Maximum Payload Size.
© 2002–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG.
DS506 April 19, 2010
www.xilinx.com
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Product Specification