DS506 Datasheet, PDF (6/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Table 1: PCI Configuration Space Header
31
16 15
Device ID
Vendor ID
Status
Command
Class Code
Rev ID
BIST
Header
Lat Timer
Cache Ln
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Cardbus CIS Pointer
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
CapPtr
Reserved
Max Lat
Min Gnt
Intr Pin
Intr Line
PM Capability
NxtCap
PM Cap
Data
BSE
PMCSR
MSI Control
NxtCap
MSI Cap
Message Address (Lower)
Message Address (Upper)
Reserved
Message Data
PE Capability
NxtCap
PE Cap
PCI Express Device Capabilities
Device Status
Device Control
PCI Express Link Capabilities
Link Status
Link Control
Next Cap
Reserved Legacy Configuration Space
(Returns 0x00000000)
Capability
PCI Exp. Capability
PCI Express Device Serial Number (1st)
PCI Express Device Serial Number (2nd)
Reserved Extended Configuration Space
(Returns Completion with UR)
0
000h
004h
008h
00Ch
010h
014h
018h
01Ch
020h
024h
028h
02Ch
030h
034h
038h
03Ch
040h
044h
048h
04Ch
050h
054h
058h
05Ch
060h
064h
068h
06Ch-0FFh
100h
104h
108h
10Ch-FFFh
6
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DS506 April 19, 2010
Product Specification