DS506 Datasheet, PDF (17/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
Figure 3 illustrates the transfer of two TLPs received on the PCI Express Link on the TRN interface.
X-Ref Target - Figure 3
trn_rsrc_rdy_n
trn_rdst_rdy_n
trn_rd[63:0]
A-D0
A-D1
A-D2
A-D3
B-D0
B-D1
trn_rsof_n
trn_reof_n
trn_rrem_n[7:0]
XX
XX
XX
00
XX
00
XX
Figure 3: Rx TRN Interface (64-bit Transaction Interface shown)
Table 10 defines and describes the receive path clock cycle signals.
Table 10: Receive Path Clock Cycle Signals
Clock Cycle
Event Description
1
The core signals by the assertion of trn_rsrc_rdy_n and trn_rsof_n that a valid TLP has been
entirely received from the link.
2
The user application asserts trn_rdst_rdy_n to signal that it is ready to receive the TLP.
3
The combined assertion of trn_rsrc_rdy_n and trn_rdst_rdy_n marks a data transfer.
5
The end of the frame is signaled with trn_reof_n.
6
The first QWORD of the second frame is transferred. The core asserts trn_rsof_n to mark the
start of the frame.
7
The end of the current frame is marked with the assertion of trn_reof_n.
8
The core deasserts its trn_rsrc_rdy_n signal because there are no more pending TLPs to
transfer.
DS506 April 19, 2010
www.xilinx.com
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Product Specification