DS506 Datasheet, PDF (10/19 Pages) Xilinx, Inc – LogiCORE IP Endpoint v3.7

LogiCORE IP Endpoint v3.7 for PCI Express^®
the state of the selected register over the 32-bit data output port. Table 6 describes the configuration
interface signals.
Table 6: Configuration Interface Signals
Name
Direction
Description
cfg_do[31:0]
Output
Configuration Data Out: A 32-bit data output port used to
obtain read data from the configuration space inside the core.
cfg_rd_wr_done_n
Output
Configuration Read Write Done: Active-low, read-write done
signal indicates a successful completion of the user
configuration register access operation.
• For a user configuration register read operation, the signal
validates the cfg_do[31:0] data-bus value.
• For a user configuration register write operation, the
assertion signals completion of a successful write operation.
Not supported for write operations.
cfg_di[31:0]
Input
Configuration Data In: A 32-bit data input port used to provide
write data to the configuration space inside the core.
Unimplemented, reserved for future use.
cfg_dwaddr[9:0]
Input
Configuration DWORD Address: A 10-bit address input port
used to provide a configuration register DWORD address
during configuration register accesses.
cfg_interrupt_n
Input
Configuration Interrupt: Active-low interrupt-request signal.
The User Application may assert this to cause the selected
interrupt message-type to be transmitted by the core. The
signal should be held low until cfg_interrupt_rdy_n is asserted.
cfg_interrupt_rdy_n
Output
Configuration Interrupt Ready: Active-low interrupt grant
signal. The simultaneous assertion of cfg_interrupt_rdy_n and
cfg_interrupt_n indicates that the core has successfully
transmitted the requested interrupt message.
cfg_interrupt_mmenable[2:0]
Output
Configuration Interrupt Multiple Message Enable: This is
the value of the Multiple Message Enable field. Values range
from 000b to 101b. A value of 000b indicates that single vector
MSI is enabled, while other values indicate the number of bits
that may be used for multi-vector MSI.
cfg_interrupt_msienable
Output
Configuration Interrupt MSI Enabled: Indicates that the
Message Signaling Interrupt (MSI) messaging is enabled. If 0,
then only Legacy (INTx) interrupts may be sent.
cfg_interrupt_di[7:0]
Input
Configuration Interrupt Data In: For Message Signaling
Interrupts (MSI), the portion of the Message Data that the
endpoint must drive to indicate MSI vector number, if Multi-
Vector Interrupts are enabled. The value indicated by
cfg_interrupt_mmenable[2:0] determines the number of lower-
order bits of Message Data that the endpoint provides; the
remaining upper bits of cfg_interrupt_di[7:0] are not used. For
Single-Vector Interrupts, cfg_interrupt_di[7:0] is not used. For
Legacy interrupt messages (Assert_INTx, Deassert_INTx), the
following list defines the type of message to be sent:
Value
Legacy Interrupt
00h
INTA
01h
INTB
02h
INTC
03h
INTD
cfg_interrupt_do[7:0]
Output
Configuration Interrupt Data Out: The value of the lowest 8
bits of the Message Data field in the endpoint's MSI capability
structure. This value is used in conjunction with
cfg_interrupt_mmenable[2:0] to drive cfg_interrupt_di[7:0].
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DS506 April 19, 2010
Product Specification