XC2VP2 Datasheet, PDF (85/430 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
RocketIO Switching Characteristics
Table 22: RocketIO X Reference Clock Switching Characteristics
Description
Reference Clock frequency range⁽¹⁾
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak
Symbol
F_GCLK
F_GTOL
T_RCLK
T_FCLK
T_DCREF
T_GJTT
Conditions
20% – 80%
20% – 80%
3.125 Gb/s – 6.25 Gb/s
2.488 Gb/s – 3.125 Gb/s
Clock recovery frequency acquisition time,
from Power-up to High state of PMARXLOCK
T_LOCK
Clock recovery phase acquisition time,
from Data to High state of PMARXLOCK
T_PHASE
Notes:
1. BREFCLK should be used for all serial bit rates up to the maximum shown.
All Speed Grades
Min Typ Max
62.5
425
±350
75
75
45
50
55
30
40
100
40
60
Units
MHz
ppm
ps
ps
%
ps
ps
µs
µs
Table 23: RocketIO Reference Clock Switching Characteristics
All Speed Grades
Description
Symbol
Conditions
Min Typ Max
Units
Reference Clock frequency range⁽¹⁾
Full rate operation
50
F_GCLK
Half rate operation⁽²⁾
(2X oversampling)
60
156.25
100
MHz
MHz
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak⁽³⁾
F_GTOL
±100
T_RCLK
20% – 80%
600 1000
T_FCLK
20% – 80%
600 1000
T_DCREF
45
50
55
2.501 Gb/s – 3.125 Gb/s
40
T_GJTT
1.061 Gb/s – 2.5 Gb/s
50
< 1.06 Gb/s
120
ppm
ps
ps
%
ps
ps
ps
Clock recovery frequency acquisition time
Clock recovery phase acquisition time
T_LOCK
T_PHASE
10
960
µs
bits ⁽⁴⁾
Notes:
1. BREFCLK/BREFCLK2 can be used for all serial bit rates up to the maximum shown. REFCLK/REFCLK2 can be used for serial bit rates up to
2.5 Gb/s (REFCLK = 125 MHz). All other parameters apply equally to REFCLK, REFCLK2, BREFCLK, and BREFCLK2 except as noted.
2. For serial rates under 1 Gb/s, the 3X (or greater) oversampling techniques described in XAPP572 are required to meet the transmit jitter and
receive jitter tolerance specifications defined in this data sheet.
3. Measured at the package pin. For reference clock frequencies equal to or above 125 MHz, BREFCLK/BREFCLK2 must be used.
4. 8B/10B-type bitstream.
T_RCLK
80%
20%
T_FCLK
DS083-3_01_120302
Figure 3: Reference Clock Timing Parameters
DS083 (v4.7) November 5, 2007
Product Specification
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