XC2VP2 Datasheet, PDF (42/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
High pin count packages (especially ball grid arrays) can
not accommodate external termination resistors.
Virtex-II Pro XCITE DCI provides controlled impedance
drivers and on-chip termination for single-ended and differ-
ential I/Os. This eliminates the need for external resistors
and improves signal integrity. The DCI feature can be used
on any IOB by selecting one of the DCI I/O standards.
When applied to inputs, DCI provides input parallel termina-
tion. When applied to outputs, DCI provides controlled
impedance drivers (series termination) or output parallel
termination.
DCI operates independently on each I/O bank. When a DCI
I/O standard is used in a particular I/O bank, external refer-
ence resistors must be connected to two dual-function pins
on the bank. These resistors, voltage reference of N transis-
tor (VRN) and the voltage reference of P transistor (VRP)
are shown in Figure 26.
Controlled Impedance Drivers (Series Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z₀). Virtex-II Pro
input buffers also support LVDCI and LVDCI_DV2.
IOB
Z
Z₀
Virtex-II Pro DCI
V_CCO = 3.3V, 2.5 V, 1.8 V, or 1.5 V
DS083-2_09_082902
Figure 27: Internal Series Termination
Table 13: SelectIO-Ultra Controlled Impedance Buffers
V_CCO
3.3V
DCI
LVDCI_33
DCI Half Impedance
N/A
2.5V
LVDCI_25
LVDCI_DV2_25
1.8V
LVDCI_18
LVDCI_DV2_18
1.5V
LVDCI_15
LVDCI_DV2_15
1 Bank
DCI
DCI
DCI
DCI
VCCO
VRN
VRP
R_REF (1%)
R_REF (1%)
GND
DS031_50_101200
Figure 26: DCI in a Virtex-II Pro Bank
When used with a terminated I/O standard, the value of the
resistors are specified by the standard (typically 50Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (20Ω to 100Ω). For all series and parallel termina-
tions listed in Table 13 and Table 14, the reference resistors
must have the same value for any given bank. One percent
resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
Controlled Impedance Terminations (Parallel)
DCI also provides on-chip termination for SSTL2, SSTL18,
HSTL (Class I, II, III, or IV), LVDS_25, LVDSEXT_25, and
GTL/GTLP receivers or transmitters on bidirectional lines.
Table 14 and Table 15 list the on-chip parallel terminations
available in Virtex-II Pro devices. V_CCO must be set accord-
ing to Table 10. There is a V_CCO requirement for GTL_DCI
and GTLP_DCI, due to the on-chip termination resistor.
Table 14: SelectIO-Ultra Buffers With On-Chip Parallel
Termination
IOSTANDARD Attribute
I/O Standard
Description
External
Termination
On-Chip
Termination
SSTL Class I, 2.5V
SSTL Class II, 2.5V
SSTL2_I
SSTL2_II
SSTL2_I_DCI⁽¹⁾
SSTL2_II_DCI ⁽¹⁾
SSTL Class I, 1.8V
SSTL18_I
SSTL18_I_DCI
SSTL Class II, 1.8V
SSTL18_II
SSTL18_II_DCI
HSTL Class I
HSTL_I
HSTL_I_DCI
HSTL Class I, 1.8V
HSTL_I_18
HSTL_I_DCI_18
HSTL Class II
HSTL_II
HSTL_II_DCI
HSTL Class II, 1.8V
HSTL_II_18
HSTL_II_DCI_18
HSTL Class III
HSTL_III
HSTL_III_DCI
HSTL Class III, 1.8V HSTL_III_18 HSTL_III_DCI_18
HSTL Class IV
HSTL_IV
HSTL_IV_DCI
HSTL Class IV, 1.8V HSTL_IV_18 HSTL_IV_DCI_18
GTL
GTL
GTL_DCI
GTL Plus
GTLP
GTLP_DCI
Notes:
1. SSTL compatible.
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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