XC2VP2 Datasheet, PDF (31/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
The Trace port provides instruction execution trace informa-
tion to an external trace tool. The PPC405 core is capable of
back trace and forward trace. Back trace is the tracing of
instructions prior to a debug event while forward trace is the
tracing of instructions after a debug event.
The processor JTAG port and the FPGA JTAG port can be
accessed independently, or the two can be programmati-
cally linked together and accessed via the dedicated FPGA
JTAG pins.
For detailed information on the PPC405 JTAG interface,
please refer to the "JTAG Interface" section of the PowerPC
405 Processor Block Reference Guide
CoreConnect™ Bus Architecture
The Processor Block is compatible with the CoreConnect™
bus architecture. Any CoreConnect compliant cores includ-
ing Xilinx soft IP can integrate with the Processor Block
through this high-performance bus architecture imple-
mented on FPGA fabric.
The CoreConnect architecture provides three buses for
interconnecting Processor Blocks, Xilinx soft IP, third party
IP, and custom logic, as shown in Figure 15:
System
Core
System
Core
System ^DCR Peripheral Peripheral
Core ^Bus Core
Core
Processor Local Bus
Instruction
Data
Bus
Bridge
On-Chip Peripheral Bus
CoreConnect Bus Architecture
Processor
Block
DCR Bus
DS083-2_02a_010202
Figure 15: CoreConnect Block Diagram
• Processor Local Bus (PLB)
• On-Chip Peripheral Bus (OPB)
• Device Control Register (DCR) bus
High-performance peripherals connect to the high-band-
width, low-latency PLB. Slower peripheral cores connect to
the OPB, which reduces traffic on the PLB, resulting in
greater overall system performance.
For more information, refer to:
http://www-3.ibm.com/chips/techlib/techlib.nfs/productfa
milies/CoreConnect_Bus_Architecture/
Functional Description: Embedded PowerPC 405 Core
This section offers a brief overview of the various functional blocks shown in Figure 16.
PLB Master
Interface
Instruction
OCM
I-Cache I-Cache
Array Controller
Instruction
Cache
Unit
MMU
Instruction Shadow
TLB
(4 Entry)
Cache Units
Data
Cache
Unit
D-Cache D-Cache
Array Controller
Unified TLB
(64 Entry)
Data Shadow
TLB
(8 Entry)
Fetch & Decode
3-Element
Fetch Fetch
and Queue
Decode (PFB1,
Logic PFB0,
DCD)
Execution Unit (EXU)
32 x 32
GPR
ALU
MAC
Execution Unit
Timers
(FIT,
PIT,
Watchdog)
Timers
&
Debug
Debug Logic
PLB Master
Interface
Data
OCM
JTAG Instruction
Trace
DS083-2_01_062001
Figure 16: Embedded PPC405 Core Block Diagram
Embedded PPC405 Core
The embedded PPC405 core is a 32-bit Harvard architec-
ture processor. Figure 16 illustrates its functional blocks:
• Cache units
• Memory Management unit
• Fetch Decode unit
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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