XC2VP2 Datasheet, PDF (69/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as DCI.
Readback
In this mode, configuration data from the Virtex-II Pro FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary-Scan mode.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM+, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II Pro Platform FPGA User Guide.
Bitstream Encryption
Virtex-II Pro devices have an on-chip decryptor using one or
two sets of three keys for triple-key Data Encryption Stan-
dard (DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V_BATT pin, when the
device is not powered. Virtex-II Pro devices can be config-
ured with the corresponding encrypted bitstream, using any
of the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II Pro Platform FPGA User Guide.
Your local FAE can also provide specific information on this
feature.
Partial Reconfiguration
Partial reconfiguration of Virtex-II Pro devices can be
accomplished in either Slave SelectMAP mode or Bound-
ary-Scan mode. Instead of resetting the chip and doing a
full configuration, new data is loaded into a specified area of
the chip, while the rest of the chip remains in operation.
Data is loaded on a column basis, with the smallest load unit
being a configuration “frame” of the bitstream (device size
dependent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
For more information on Partial Reconfiguration in
Virtex-II Pro devices, please refer to Xilinx Application Note
XAPP290, Two Flows for Partial Reconfiguration.
Revision History
This section records the change history for this module of the data sheet.
Date
01/31/02
06/13/02
09/03/02
09/27/02
11/20/02
12/03/02
01/20/03
Version
1.0
2.0
2.1
2.2
2.3
2.4
2.5
Revision
Initial Xilinx release.
New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
• Revised Reset and Power sections.
• Updated Table 8, which lists compatible input standards. [Table deleted in v2.6.]
• Added Figure 28, Figure 29, and Figure 30, which provide examples illustrating the
use of I/O standards.
• In section RocketIO Overview, corrected max number of MGTs from 16 to 24.
• In section Input/Output Blocks (IOBs), added references to XAPP653 regarding
implementation of 3.3V I/O standards.
• Table 8: Added rows for LVTTL, LVCMOS33, and PCI-X.
• Table 8: Added LVTTL and LVCMOS33 to compatible 3.3V cells. [Table deleted in
v2.6.]
• Table 33: Correct bitstream lengths.
• Added mention of LVTTL and PCI with respect to SelectIO-Ultra configurations. See
section Input/Output Individual Options and Figure 22.
• Added qualification to features vs. Virtex-II (open-drain output pin TDO does not have
internal pull-up resistor)
• Table 7: Added HSTL18 (I, II, III, & IV) and HSTL18_DCI (I,II, III & IV) to 1.8V VCCO
row. [Table deleted in v2.6.]
• Table 8: Numerous revisions. [Table deleted in v2.6.]
DS083 (v4.7) November 5, 2007
Product Specification
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