XC2VP2 Datasheet, PDF (258/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
FF1148 Flip-Chip Fine-Pitch BGA Package
As shown in Table 11, XC2VP40 and XC2VP50 Virtex-II Pro devices are available in the FF1148 flip-chip fine-pitch BGA
package. Pins in each of these devices are the same, except for the differences shown in the No Connect column. Following
this table are the FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 11: FF1148 — XC2VP40 and XC2VP50
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Description
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
IO_L02P_0
IO_L03N_0
IO_L03P_0/VREF_0
IO_L05_0/No_Pair
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0/VREF_0
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0
IO_L27N_0
IO_L27P_0/VREF_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
Pin Number
E25
F25
J24
K24
C25
D25
G25
A25
B25
G24
G23
H23
H22
E24
F24
C24
C23
J23
K23
A24
B24
E23
F23
K22
L22
D23
D22
A23
B23
J21
J20
F22
G22
No Connects
XC2VP40
XC2VP50
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
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