XC2VP2 Datasheet, PDF (410/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Table 14: FF1696 — XC2VP100
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
Pin Description
IO_L45N_7
IO_L44P_7
IO_L44N_7
IO_L43P_7
IO_L43N_7
IO_L42P_7
IO_L42N_7
IO_L41P_7
IO_L41N_7
IO_L40P_7
IO_L40N_7/VREF_7
IO_L39P_7
IO_L39N_7
IO_L38P_7
IO_L38N_7
IO_L37P_7
IO_L37N_7
IO_L36P_7
IO_L36N_7
IO_L35P_7
IO_L35N_7
IO_L34P_7
IO_L34N_7/VREF_7
IO_L33P_7
IO_L33N_7
IO_L32P_7
IO_L32N_7
IO_L31P_7
IO_L31N_7
IO_L30P_7
IO_L30N_7
IO_L29P_7
IO_L29N_7
IO_L28P_7
IO_L28N_7/VREF_7
IO_L27P_7
IO_L27N_7
Pin Number
T36
W32
W33
R41
R42
P40
R40
V36
V37
R38
R39
P38
R37
V34
V35
P41
P42
P36
P37
V32
V33
M41
N41
N39
N40
U35
U36
N36
N37
M39
M40
U32
U33
M37
M38
L37
M36
No Connects
XC2VP100
DS083 (v4.7) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
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