XC2VP2 Datasheet, PDF (58/430 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
3. NO_CHANGE
The NO_CHANGE option maintains the content of the out-
put registers, regardless of the write operation. The clock
edge during the write mode has no effect on the content of
the data output register DO. When the port is configured as
NO_CHANGE, only a read operation loads a new value in
the output register DO, as shown in Figure 51.
Data_in
Internal
DI _Memory
DO
No change during write
CLK
WE
Data_in
New
Address
aa
RAM Contents
Old
New
Data_out
Last Read Cycle Content (no change)
DS083-2_12_050901
Figure 51: NO_CHANGE Mode
Control Pins and Attributes
Virtex-II Pro SelectRAM+ memory has two independent
ports with the control signals described in Table 24. All con-
trol inputs including the clock have an optional inversion.
Table 24: Control Functions
Control Signal
Function
CLK
Read and Write Clock
EN
Enable affects Read, Write, Set, Reset
WE
Write Enable
SSR
Set DO register to SRVAL (attribute)
Table 25 shows the number of columns as well as the total
amount of block SelectRAM+ memory available for each
Virtex-II Pro device. The 18 Kb SelectRAM+ blocks are
cascadable to implement deeper or wider single- or dual-port
memory resources.
Table 25: Virtex-II Pro SelectRAM+ Memory Available
Total SelectRAM+ Memory
Device Columns Blocks in Kb in Bits
XC2VP2
4
12
216
221,184
XC2VP4
4
28
504
516,096
XC2VP7
6
44
792
811,008
XC2VP20
8
88 1,584 1,622,016
XC2VP30
8
136 2,448 2,506,752
XC2VPX20
8
88 1,584 1,622,016
XC2VP40
10
192 3,456 3,538,944
XC2VP50
12
232 4,176 4,276,224
XC2VP70
14
328 5,904 6,045,696
XC2VPX70
14
308 5,544 5,677,056
XC2VP100
16
444 7,992 8,183,808
Figure 52 shows the layout of the block RAM columns in the
XC2VP4 device.
DCM
RocketIO^TM
Serial Transceivers
DCM
BRAM
Multiplier
Blocks
CLBs
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM+ resource is config-
ured as dual-port RAM.
Total Amount of SelectRAM+ Memory
Virtex-II Pro SelectRAM+ memory blocks are organized in
multiple columns. The number of blocks per column
depends on the row size, the number of Processor Blocks,
and the number of RocketIO transceivers.
CLBs CLBs ^PPC405
CPU
DCM
RocketIO^TM
DCM
Serial Transceivers _{DS083-2_11_010802}
Figure 52: XC2VP4 Block RAM Column Layout
DS083 (v4.7) November 5, 2007
Product Specification
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