W942508CH Datasheet, PDF (8/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
Input/Output Voltage
VIN, VOUT
-0.3 − VDDQ +0.3
V
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
VDD, VDDQ
-0.3 − 3.6
V
TOPR
0 − 70
°C
TSTG
-55 − 150
°C
TSOLDER
260
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
7.2 Recommended DC Operating Conditions
(TA = 0 to 70 °C)
SYMBOL
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
VICK (DC)
VID (DC)
PARAMETER
Power Supply Voltage
Power Supply Voltage
(for I/O Buffer)
Input reference Voltage
Termination Voltage (System)
Input High Voltage (DC)
Input Low Voltage (DC)
Differential Clock DC Input
Voltage
Input Differential Voltage.
CLK and CLK inputs (DC)
VIH (AC)
VIL (AC)
VID (AC)
Input High Voltage (AC)
Input Low Voltage (AC)
Input Differential Voltage.
CLK and CLK inputs (AC)
VX (AC)
VISO (AC)
Differential AC input Cross
Point Voltage
Differential Clock AC Middle
Point
MIN.
2.3
2.3
0.49 x VDDQ
VREF -0.04
VREF +0.15
-0.3
-0.3
0.36
VREF +0.31
-
0.7
VDDQ/2 -0.2
VDDQ/2 -0.2
TYP.
2.5
2.5
0.50 x VDDQ
VREF
-
-
-
-
-
-
-
-
-
Notes: Undershoot Limit: VIL (min) = -0.9V with a pulse width < 5 nS
Overshoot Limit: VIH (max) = VDDQ +0.9V with a pulse width < 5 nS
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
VIH (AC) and VIL (AC) are levels to change to the new logic state.
MAX.
2.7
VDD
0.51 x VDDQ
VREF +0.04
VDDQ +0.3
VREF -0.15
VDDQ +0.3
VDDQ +0.6
-
VREF -0.31
VDDQ +0.6
VDDQ/2 +0.2
VDDQ/2 +0.2
UNIT NOTES
V
2
V
2
V
2, 3
V
2, 8
V
2
V
2
V
15
V
13, 15
V
2
V
2
V
13, 15
V
12, 15
V
14, 15
-8-