W942508CH Datasheet, PDF (10/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
7.5 DC Characteristics
SYM.
PARAMETER
MAX.
UNIT NOTES
-5
-6
-7 -75
OPERATING CURRENT: One Bank Active-Precharge; tRC =
IDD0
tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice
per clock cycle; Address and control inputs changing once per
110
110 110 110
7
clock cycle
OPERATING CURRENT: One Bank Active-Read-Precharge;
IDD1 Burst = 2; tRC = tRC min; CL = 2.5; tCK = tCK min; IOUT = 0 mA;
120 120 120 120
7, 9
Address and control inputs changing once per clock cycle.
PRECHARGE-POWER-DOWN STANDBY CURRENT: All
IDD2P Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min;
Vin = VREF for DQ, DQS and DM
8
8
8
8
IDLE FLOATING STANDBY CURRENT: CS > VIH min; All
IDD2F _{Banks Idle; CKE > VIH min; Address and other control inputs}
45 45 45 40
7
changing once per clock cycle; Vin = Vref for DQ, DQS and DM
IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle;
IDD2N ^{CKE > VIH min; tCK = tCK min; Address and other control inputs}
45
45
45
40
7
changing once per clock cycle; Vin > VIH min or Vin < VIL max
for DQ, DQS and DM
IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks
IDD2Q _{Idle; CKE > VIH min; tCK = tCK min; Address and other control}
40 40 40 35
7
inputs stable; Vin > VREF for DQ, DQS and DM
mA
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank
Active; Power down mode; CKE < VIL max; tCK = tCK min
20 20 20 20
ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH
IDD3N ^{min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min;} 70
70
70
65
7
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
IDD4R One Bank Active; Address and control inputs changing once
165 165 165 155
7, 9
per clock cycle; CL=2.5; tCK = tCK min; IOUT = 0mA
OPERATING CURRENT: Burst = 2; Write; Continuous burst;
IDD4W
One Bank Active; Address and control inputs changing once
per clock cycle; CL = 2.5; tCK = tCK min; DQ, DM and DQS
165 165 165 155
7
inputs changing twice per clock cycle
IDD5 AUTO REFRESH CURRENT: tRC = tRFC min
190 190 190 190
7
IDD6 SELF REFRESH CURRENT: CKE < 0.2V
9
9
9
9
RANDOM READ CURRENT: 4 Banks Active Read with
IDD7
activate every 20ns, Auto-Precharge Read every 20 nS; Burst =
4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing
270
270
270
270
twice per clock cycle; Address changing once per clock cycle
tCK = 10ns
CK
CK
COMMAND ACT
ADDRESS
Bank 0
Row d
DQS
tRCD
READ
AP
ACT
Bank 3
RCoowl cc
Bank 1
Row e
READ
AP
Bank 0
RCoowl dd
tRC
ACT
Bank 2
Row f
READ
AP
Bank 1
RCoowl ee
ACT
Bank 3
Row q
READ
AP
Bank 2
Col f
ACT
Bank 0
Row h
DQ
Qa Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd Qd Qd Qe Qe
RANDOM READ CURRENT Timing (IDD7)
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