W942508CH Datasheet, PDF (29/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
CLK
CLK
CS
tCK
tIS
tIH
tCH
tCL
RAS
CAS
WE
tIS
tIH
tIS
tIH
tIS
tIH
A0~A12
BS0, 1
tIS
tIH
Refer to the Command Truth Table
10.2 Timing of the CLK Signals
CLK
tCH
tCL
CLK
tT
tT
tCK
CLK
CLK
VX
VX
VX
VIH
VIH(AC)
VIL(AC)
VIL
VIH
VIL
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Publication Release Date: May 21, 2003
Revision A3