W942508CH Datasheet, PDF (3/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
1. GENERAL DESCRIPTION
W942508CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 8,388,608 words × 4 banks × 8 bits. Using pipelined architecture and 0.13 µm
process technology, W942508CH delivers a data bandwidth of up to 400M words per second (-5). To
fully comply with the personal computer industrial standard, W942508CH is sorted into four speed
grades: -5, -6, -7, -75 The -5 is compliant to the 200MHz/CL2.5 & CL3 specification, The -6 is
compliant to the 166MHz/CL2.5 specification, the -7 is compliant to the 143MHz/CL2.5 or
DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification.
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942508CH is ideal for main memory in
high performance applications.
2. FEATURES
• 2.5V ±0.2V Power Supply for DDR266
• 2.5V ±0.2V Power Supply for DDR333
• 2.6V ±0.1V Power Supply for DDR400
• Up to 200 MHz Clock Frequency
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and CLK )
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 2, 2.5 and 3
• Burst Length: 2, 4 and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power Down
• Write Data Mask
• Write Latency = 1
• 8K Refresh cycles / 64 mS
• Interface: SSTL-2
• Packaged in TSOP II 66-pin, 400 x 875mil, 0.65mm pin pitch
Publication Release Date: May 21, 2003
-3-
Revision A3