W942508CH Datasheet, PDF (6/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME
28 − 32,
35 − 42
A0 − A12
26, 27
BS0, BS1
2, 5, 8, 11, 56,
59, 62, 65
DQ0 − DQ7
51
DQS
24
CS
FUNCTION
Address
Bank Select
Data Input/
Output
Data Strobe
Chip Select
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 − A12.
Column address: A0 − A9. (A10 is used for Auto Precharge)
Select bank to activate during row address latch time, or bank
to read/write during column address latch time.
The DQ0 – DQ7 input and output data are synchronized with
both edges of DQS.
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
RAS , CAS ,
WE
Command Command inputs (along with CS ) define the command being
Inputs
entered.
47
DM
Write Mask
When DM is asserted "high" in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45, 46
CLK, CLK
All address and control input signals are sampled on the
Differential _{crossing of the positive edge of CLK and negative edge of}
Clock Inputs _{CLK .}
CKE controls the clock activation and deactivation. When CKE
44
CKE
Clock Enable is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
49
VREF
Reference
Voltage
VREF is reference voltage for inputs.
1, 18, 33
VDD
Power (+2.5) Power for logic circuit inside DDR SDRAM.
34, 48, 66
VSS
Ground Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
VDDQ
Power (+2.5V) Separated power from VDD, used for output buffer, to improve
for I/O Buffer noise.
6, 12, 52, 58, 64 VSSQ
Ground for I/O Separated ground from VSS, used for output buffer, to improve
Buffer
noise.
4, 7, 10, 13, 14,
16, 17, 19, 20,
25, 43, 50, 53,
54, 57, 60, 63
NC1, NC2
No Connection No connection
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