W942508CH Datasheet, PDF (28/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
(3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the
first data read. The minimum values of CAS Latency depends on the frequency of CLK.
A6 A5 A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
(4) DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
(5) Mode Register /Extended Mode register change bits (BS0, BS1)
These bits are used to select MRS/EMRS.
BS1 BS0
A12-A0
0
0
Regular MRS Cycle
0
1
Extended MRS Cycle
1
x
Reserved
(6) Extended Mode Register field
1) DLL Switch field (A0)
This bit is used to select DLL enable or disable
A0
DLL
0
Enable
1
Disable
2) Output Driver Size Control field (A1)
This bit is used to select Output Driver Size, both Full strength and Half strength are based on
JEDEC standard.
A1
OUTPUT DRIVER
0
Full Strength
1
Half Strength
(7) Reserved field
• Test mode entry bit (A7)
This bit is used to enter Test mode and must be set to "0" for normal operation.
• Reserved bits (A9, A10, A11, A12)
These bits are reserved for future operations. They must be set to "0" for normal operation.
- 28 -