W942508CH Datasheet, PDF (43/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
Timing Waveforms, continued
10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
CMD
ACTa
tRRD
tRRD
ACTb
tRCD(a)
tRAS(a)
tRC(a)
tRRD
tRRD
ACTc READAa ACTd READAb ACTa READAc
tRCD(b)
tRAS(b)
tRP
tRCD(c)
tRAS(c)
tRCD(d)
tRAS(d)
DQS
DQ
CL(a)
Preamble Postamble Preamble
CL(b)
Q0a Q1a
Q0b Q1b
ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK
CLK
CMD
ACTa
tRRD
tRRD
tRC(a)
tRRD
tRRD
ACTb READAa ACTc READAb ACTd READAc ACTa READAd
tRCD(a)
tRAS(a)
tRCD(b)
tRAS(b)
tRCD(c)
tRAS(c)
tRP(a)
tRCD(d)
tRAS(d)
DQS
DQ
Preamble
CL(a)
CL(bc)
CL(b)
Q0a Q1a Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
APc
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Publication Release Date: May 21, 2003
Revision A3