W942508CH Datasheet, PDF (11/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
7.6 AC Characteristics and Operating Condition
(Notes: 10, 12)
SYM.
tRC
tRFC
tRAS
tRCD
tRAP
tCCD
tRP
tRRD
tWR
tDAL
tCK
PARAMETER
Active to Ref/Active Command Period
Ref to Ref/Active Command Period
Active to Precharge Command Period
Active to Read/Write Command Delay Time
Active to Read with Auto Precharge Enable
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
Auto Precharge Write Recovery + Precharge Time
CLK Cycle Time
CL = 2
CL = 2.5
-7
MIN. MAX.
65
75
45 100000
20
15
1
20
15
15
30
7.5
15
7
15
-75
MIN. MAX.
65
75
45 100000
20
15
1
20
15
15
30
8
15
7.5
15
UNITS NOTES
nS
tCK
nS
tAC
Data Access Time from CLK, CLK
-0.75 0.75 -0.75 0.75
16
tDQSCK _{DQS Output Access Time from CLK, CLK}
-0.75 0.75 -0.75 0.75
tDQSQ Data Strobe Edge to Output Data Edge Skew
0.5
0.5
tCH
CLk High Level Width
tCL
CLK Low Level Width
0.45 0.55 0.45 0.55
tCK
11
0.45 0.55 0.45 0.55
tHP
CLK Half Period (minimum of actual tCH, tCL)
Min.
(tCL,tCH)
Min.
(tCL,tCH)
nS
tQH
DQ Output Data Hold Time from DQS
THP
-0.75
THP
-0.75
tRPRE
tRPST
DQS Read Preamble Time
DQS Read Postamble Time
0.9
1.1
0.9
1.1
tCK
11
0.4
0.6
0.4
0.6
tDS
DQ and DM Setup Time
tDH
DQ and DM Hold Time
0.5
0.5
0.5
0.5
nS
tDIPW DQ and DM Input Pulse Width (for each input)
1.75
1.75
tDQSH DQS Input High Pulse Width
0.35
0.35
tDQSL
tDSS
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
0.35
0.35
0.2
0.2
tCK
11
tDSH DQS Falling Edge Hold Time from CLK
0.2
0.2
tWPRES Clock to DQS Write Preamble Set-up Time
0
0
nS
tWPRE
tWPST
tDQSS
DQS Write Preamble Time
DQS Write Postamble Time
Write Command to First DQS Latching Transition
0.25
0.25
0.4
0.4
11
tCK
0.75 1.25 0.75 1.25
tDSSK UDQS – LDQS Skew (x 16)
-0.25 0.25 -0.25 0.25
tIS
Input Setup Time
0.9
0.9
tIH
Input Hold Time
0.9
0.9
tIPW Control & Address Input Pulse Width (for each input) 2.2
2.2
tHZ
Data-out High-impedance Time from CLK, CLK
-0.75 0.75 -0.75 0.75
nS
tLZ
tT(SS)
tWTR
tXSNR
tXSRD
tREF
tMRD
Data-out Low-impedance Time from CLK, CLK
SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
Refresh Time (8k)
Mode Register Set Cycle Time
-0.75 0.75 -0.75 0.75
0.5
1.5
0.5
1.5
1
1
tCK
75
75
ns
10
10
tCK
64
64
mS
15
15
nS
- 11 -
Publication Release Date: May 21, 2003
Revision A3