W942508CH Datasheet, PDF (14/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF and must track variations in the DC level of VREF.
(9) These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min.(AC) and VIL max.(AC).Transition (rise and fall) of input signals have
a fixed slope.
(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., tDQSS = 0.75 × tCK, Tck = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK)+VICK( CLK )}/2.
(15) Refer to the figure below.
CLK
VX
CLK
VICK
VSS
VID(AC)
0 V Differential
VISO
VSS
VX
VICK
VISO(min)
VX
VICK
VX
VICK
VX
VID(AC)
VISO(max)
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
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