W942508CH Datasheet, PDF (27/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
• Address Sequence of Sequential Mode
A column access is performed by incrementing the column address input to the device. The
address is varied by the Burst Length as the following.
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Addressing Sequence of Sequential Mode
ACCESS ADDRESS
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BURST LENGTH
2 words (address bits is A0)
not carried from A0 to A1
4 words (address bit A0, A1)
Not carried from A1 to A2
8 words (address bits A2, A1 and A0)
Not carried from A2 to A3
• Addressing Sequence of Interleave Mode
A Column access is started from the inputted column address and is performed by
interleaving the address bits in the sequence shown as the following.
9.9.1.1
Address Sequence for Interleave Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BURST LENGTH
2 words
4 words
8 words
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Publication Release Date: May 21, 2003
Revision A3