W942508CH Datasheet, PDF (33/47 Pages) Winbond – 8M x 4 BANKS x 8 BIT DDR SDRAM

W942508CH
Timing Waveforms, continued
10.7 Mode Register Set (MRS) Timing
CLK
CLK
CMD
MRS
tMRD
NEXT CMD
ADD
Register Set data
A0
A1
Burst Length
A2
A3
Addressing Mode
A4
A5
CAS Latency
A6
A7 "0"
A8
Reserved
DLL Reset
A9 "0"
A10 "0"
A11 "0"
Reserved
A12 "0"
BS0 "0" _{Mode Register Set or}
Extended Mode Register
BS1 "0" ^Set
* "Reserved" should stay "0" during
MRS cycle.
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A3
0
1
A6
A5
A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A8
0
1
BS1
BS0
0
0
0
1
1
0
1
1
Burst Length
Sequential
Interleaved
Reserved
Reserved
2
2
4
4
8
8
Reserved
Reserved
Addressing Mode
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
2.5
Reserved
DLL Reset
No
Yes
MRS or EMRS
Regular MRS cycle
Extended MRS cycle
Reserved
- 33 -
Publication Release Date: May 21, 2003
Revision A3