W681307 Datasheet, PDF (76/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
11.5.4
Diag_CS3
Address
0x1473
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
RESERVED
Bit 6
Bit 5
RESERVED RD_WR_BLK
Bit 4
CS2_WAIT
_EN
Bit 3
CS3_SEL[1]
Bit 2
Bit 1
Bit 0
CS3_SEL[0] PWR_SAVE[1] PWR_SAVE[0]
/ WR
/ RD
/ CS3
3
2
Pin Name
/ CS3
1
0
0x 1473[3:2]
Figure 11-5 CS3 Output multiplexer
CS3 output multiplexer is shown in Figure 11-5. Address mapping range of CS3 is 0x2000~0x5FFF
CS3_sel[1:0]
00
01
10
11
Output
CS3
CS3 | RD
CS3 | WD
~((CS 3 | RD) & (CS3 | WR))
CS2_WAIT_EN
This is a wait state enable bit for CS2 controlled device. When set this bit, the WR/RD duration
to CS2 controlled device will last from 4 clock cycles to 8 clock cycles.
RD_WR_BLK
When set this bit, the external RD/WR signal will not active (blocked) when access internal
RAM/register (0x0000 to 0x1FFF and 0x6000 to 0x7FFF), the default is not blocked.
PWR_SAVE [1:0] You can set PWR_SAVE [1:0] to control AD/ADDR bus output state for I/O power save purpose.
PWR_SAVE[1:0]
00
01
10
11
AD/ADDR bus
No power save feature.
AD/ADDR bus only active when T8032 RD/WR in the Mask ROM mode.
AD/ADDR bus only active when T8032 RD/WR external device
(0x8000~0xFFFF),in the Mask ROM mode.
AD/ADDR bus always inactive.
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Publication Release Date: May, 2007
Revision 1.3