W681307 Datasheet, PDF (35/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
7.3.21
Address
0x1700
0x1701
0x1702
0x1703
0x1704
0x1705~
0x1707
0x1708
0x1709
0x170A
0x170B
0x170C
0x170D~
0x170F
0x1710
PCM Highway Channel Registers Overview
Name
Mode
PCM channel format and delay
control of 1st group
R/W
TX delay1
R/W
TX delay2
R/W
RX delay1
R/W
RX delay2
R/W
Reserved
PCM channel format and delay
control of 2nd group
R/W
TX delay3
R/W
TX delay4
R/W
RX delay3
R/W
RX delay4
R/W
Reserved
PCM channel format control of
2nd PCM highway
R/W
Value At
Reset
0x02
0x00
0x00
0x00
0x00
Function
PCM channel format and delay control of 1st group in the 1st
PCM Highway
Set the values for delaying the transmitted bits of PCM
channel1 after the rising edge of the Fsync.
Set the values for delaying the transmitted bits of PCM
channel2 after the tail bit of PCM channel 1.
Set the values for delaying the received bits of PCM
channel1 after the rising edge of the Fsync.
Set the values for delaying the received bits of PCM
channel2 after the tail bit of RX PCM channel 1.
0x02
0x00
0x00
0x00
0x00
PCM channel format and delay control of 2nd group in the
1st PCM Highway
Set the values for delaying the transmitted bits of PCM
channel3 after the tail bit of PCM channel 2.
Set the values for delaying the transmitted bits of PCM
channel4 after the tail bit of PCM channel 3.
Set the values for delaying the received bits of PCM
channel3 after the tail bit of RX PCM channel 2.
Set the values for delaying the received bits of PCM
channel4 after the tail bit of RX PCM channel 3.
0x02
PCM channel format control of the 2nd PCM highway.
7.3.22
Address
0x1720
0x1721
0x1722
0x1723
0x1724
0x1725
0x1726
0x1727
0x1728
SPI Interface Registers Overview
Name
SPI_control0
Mode
R/W
Value At
Reset
0x00
Function
Setting SPI interface control register.
SPI_control1
R/W
0x00
Setting SPI interface control register.
SPI Status
R
0x00
Read the SPI Status.
SPI Interrupt Enable
R/W
0x00
Enable SPI interrupt.
DumpByte
Write TX FIFO
Read RX FIFO
SPI_transfer_size
R
0x00
Show the received byte when 1720[3] is set.
W
0x00
Store data in SPI TX-FIFO when micro controller writes data
to this register.
R
0x00
Read data from SPI RX-FIFO when micro controller read data
from this register.
R/W
0x00
Setting the transfer size when Tx and Rx.
SPI_start_rtx
R/W
0x00
Start to transmit at the rate of transfer size when Tx and Rx.
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Publication Release Date: May, 2007
Revision 1.3