W681307 Datasheet, PDF (129/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
15.1.3
SPI Status
Address
0x1722
Access Mode Value At Reset Nominal Value
R
00
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
RxFIFOgeThres
hold
Bit 3
TxEmpty
Bit 2
RxEmpty
Bit 1
TxOverflow
Bit 0
RxOverflow
RxOverflow
TxOverflow
RxEmpty
TxEmpty
RxFIFOgeThreshold
When SPI keeps on receiving data and Rx-FIFO is full, the RxOverflow will be set to 1.
When 8032 writing data is fast than SPI transmitting rate, the Tx-FIFO will overflow indicated by TxOverflow bit.
Indicate the Tx-FIFO is currently empty.
Indicate the Tx-FIFO is currently empty.
When RX-FIFO reach to RxDepth_intr (0x1721[3:0]), the RxFIFOgeThreshold will set to 1.
15.1.4
SPI Interrupt Enable
Address
0x1723
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
RxInt
Bit 3
TxEmpty
Bit 2
Reserved
Bit 1
TxOverflow
Bit 0
RxOverflow
According to 0x1722, these interrupts will occur if the corresponding interrupts enable.
RxOverflow
TxOverflow
TxEmpty
RxInt
Rx overflow interrupt enable.
Tx overflow interrupt enable.
Tx empty interrupt enable. (Recommended this bit served in low data rate interface application.)
Rx interrupt enable. RX interrupt occurs upon the number of rx data reaches Rxdepth_intr[3:0].
15.1.5
DumpByte
Address
0x1724
Access Mode Value At Reset Nominal Value
R
00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DumpByte[7:0]
If 1720[3] DumpCmp is set to "1", the received byte will be filtered out (No Write to RX-FIFO) when DumpByte is equal to Received
Byte.
15.1.6
Write TX FIFO
Address
0x1725
Access Mode Value At Reset Nominal Value
W
00
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Publication Release Date: May, 2007
Revision 1.3