W681307 Datasheet, PDF (58/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
10.3.3
Status of Speech Interface When Reset
When the device is reset then the speech interface I/O pins will all be set as inputs and the associated interrupts will be masked. Resetting
the device will cause the Speech Interface Pins (PCM[0:5] to be (general purpose) I/O ports.
10.4
Internal CODEC Control
The Speech Interface Block provides two control bits to the internal CODEC. The bits are used for TxMute and DisHPF. The signals are
output from the speech interface block and go to the internal CODEC. The values output by the speech interface on the two ports equates
to the value programmed in DisHPF and TxMute, the bits are reset to 0.
10.5
PCM Interface Registers
This section describes the Speech Interface Register.
10.5.1
Speech Control 0
Address
Access Mode Value At Reset
0x1460
R/W
0x03
Nominal Value
Bit 7
Blocked
(for test modes)
Bit 6
Fsync
Advance
Bit 5
Fsync 16/8bit
Bit 4
Bit 3
Bit 2
Fsync
Long/Short
Blocked
(for test modes)
Slave Mode
Bit 1
Reserved
Bit 0
PCMH1_Dis
According to the configuration of PCMH1_Dis bit, the PCM highway function and GPIO function can be served at four PCM pins at the
same time. On the other hand, four PCM pins can just act for only pure PCM highway function or GPIO function.
B0: PCMH1_Dis
=1
=0
PCM I/O ports are GPIO function.
PCM I/O ports are serial-parallel converter function.
B2: Slave Mode
=1
=0
Effective PCM highway function will operate at slave mode.
Effective PCM highway function will operate at master mode.
B5: Fsync-16/8bit
x
0
1
B4:Fsync
Long/Short
0
1
1
Short Frame Sync signal is selected. The period of Fsync signal occupies 1 bit clock.
Long Frame Sync signal is selected. And the period of Fsync signal occupies 8 bits.
Long Frame Sync signal is selected. And the period of Fsync signal occupies 16 bits.
B6: Fsync advance
=1
=0
The PCM_FSC signal is transmitted in advance of the PCM_CLK by one system clock.
The PCM_FSC signal is transmitted at the rising edge of the PCM_CLK
10.5.2
Specific Register
Address
0x1461
Access Mode
R/W
Value At Reset
0x00
Nominal Value
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Publication Release Date: May, 2007
Revision 1.3