W681307 Datasheet, PDF (61/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
10.7
PCM Highway Interface
10.7.1
The Introduction of PCM Modes
10.7.1.1
Master / Slaver mode
For Master mode, PCM_CLK and PCM_FSC is output port.
For Slaver mode, PCM_CLK and PCM_FSC is input port.
PCM_CLK
PCM_FSC
Bitclk
.............
.............
Bitclk
PCM_IN .....Rx_DELAY1..... _{M 8/16 BITS L} ....._{Rx_DELAY2}..... _{M 8/16 BITS L} ....._{Rx_DELAY3}..... _{M 8/16 BITS L .....Rx_DELAY4..... M 8/16 BITS L}
PCM_OUT ^{.....Tx_DELAY1..... M 8/16 BITS L .....Tx_DELAY2.....} M ^{8/16 BITS} L ^{.....Tx_DELAY3.....} M ^{8/16 BITS} L ^.....Tx_DELAY4^..... M ^{8/16 BITS} L
10.7.1.2
Master mode
In master mode, PCM_CLK and PCM_FSC is output port.
PCM_FSC
PCM_CLK
PCM_IN
PCM_OUT
8K short sync or long sync.
1536 KHz
When sync is coming, it starts to catch MSB in (first sync rising + delay1 bits). LSB is depending 8bits or
16bits for first slot. Data rate is 1x or 1/2 Clk.
When sync is coming, it starts to send MSB in (first sync rising + delay1 bits). LSB is depending 8bits or
16bits for first slot. Data rate is 1x or 1/2 Clk.
PCM_CLK
(Output)
PCM_FSC
Long Sync Mode
(Output)
PCM_FSC
Short Sync Mode
(Output)
Master Mode With Data Rate = 1x CLK
PCM_IN
MSB
LSB
PCM_OUT
HI-Z
MSB
LSB
HI-Z
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Publication Release Date: May, 2007
Revision 1.3