W681307 Datasheet, PDF (15/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
90 VSS_REG PWR -
-
PVSSC Ground of 3.0V linear regulator.
91 VDD_REG PWR -
-
PVDDC 3.3V input of 3.0V linear regulator.
92
DVDD1 PWR -
93
DGND1 PWR -
1.9V linear regulator output for internal digital core power
-
PVDDC supply. Connect a large capacitor (>10uF) for output
regulation.
Digital ground 1
-
PVSSC _{(core power ground)}
94 PLL_LPF
O Tristate Tristate
Panalog
Internal 48MHz PLL charge pump output. Put a passive LPF
filter in the pin to ground.
95 VSS_USB PWR -
-
PVSSC USB analog front end ground.
USB D+ connection. Series termination resistors (22Ω±1%)
96
USB_DP
Analog
I/O
Hi-Z
Hi-Z
are required for impedance of USB bus. The USB Spec1.1
PAnalog states that the impedance of each driver is required to be
between 28 and 44Ω. This chip drive output resistance is 8 to
10Ω. Therefore, the 22Ω±1% series resistors are used.
USB D- connection. Series termination resistors (22Ω±1%)
97
USB_DN
Analog
I/O
Hi-Z
Hi-Z
are required for impedance of USB bus. The USB Spec1.1
PAnalog states that the impedance of each driver is required to be
between 28 and 44Ω. This chip drive output resistance is 8 to
10Ω. Therefore, the 22Ω±1% series resistors are used.
USB analog front end supply power. Full speed devices are
identified by pulling D+ to 3.3V±0.3 Volts via a 1.5kΩ±5 %
98 VDD_USB PWR -
-
PVDDC resistor. The baseband chip inside has been built in the
1.5kΩ±20% resistor and the default is disconnected to
VDD_USB. The
99
NC
I Input Input PC3D21 No connection
100
SNDR
O
Output Output
L
L
Sounder output - This is a control pin to turn on/off the
PC3B02U external transistor, which is used to supply the high peak
currents that magnetic sounders typically require.
* When /CS2 is pull low in the initial power on state. Then the chip will enter into the hardware ISP mode to
download the system program code via UART or USB ports.
、 ： * P1.2; P1.3 and P1.4 multiple functions
W2 S_ENA 0x1740[7] &
~(W2S_Prot_Sel 0x1740 [6])
P1. 2
0
SDA
1
P1.2
Piezo_ENB
0x144 B[ 0]
P1. 4
0
Pi ez o_CLK
1
SPI_SCK
W2S_ENA 0x1740[7 ]&
(W2 S_ Prot_Sel 0x1740[6 ])
W2S_ENA 0x1740[7 ]&
~(W2S_Prot_Sel 0x1740 [6])
P1.3
0
0
SDA
1
SCL
1
P1.3
SPI_ENB
0x1720 [7]
0
1
DF _SCK
DF _ENB
0x1730[7]
0
1
W2 S_ENA 0x1740[7] &
(W2S_ Prot_Sel 0x1740[6 ])
0
SCL
1
P1.4
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Publication Release Date: May, 2007
Revision 1.3