W681307 Datasheet, PDF (40/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
8.1
Clock Control & Reset 32K
8.1.1
Overview
、 Each register in the Speech Processor Support and Interface Logic is reset synchronously. The Reset & Clock Control function
ensures that the system reset signal is correctly generated. The system reset signal is also used to ensure that bi-directional signals are all
set to input during initialization. A separate reset signal is provided for registers operating at 32KHz.
The MCU chip has five internal 13.824MHz clocks. The clocks are gated to conserve power. Four clocks are of the same phase
and should be balanced during layout to allow data to be handled between the clock domains without additional logic. The clock to the
8032Turbo is of the opposite phase to the other four 13.824MHz clocks. The 32KHz clock is not gated or controlled on-chip.
8.1.2
Functionality
The System Reset signal SysReset is used to synchronously reset all the latches, which run from the 13.824MHz system clock:
• Two asynchronous latches sample the reset input. These are clocked to the non-reset state when the system clock is running and
are used to ensure that the device is reset if the system clock is not running when the reset input is released.
• All gated clocks are enabled and the SysReset signal is asserted for 4 system clock cycles after the end of the external reset
signal is detected by the asynchronous latches.
• SysReset is asserted from the time the asynchronous latches are reset until the end of the reset sequence to ensure bi-directional
signals are forced to safe values during initialization.
A separate latch, controlled by a processor register bit Reset32k holds all 32768Hz logic in reset until set by the processor.
The 8032T is reset by SysReset.
Clock gating is performed with an OR function such that the clock signal is held high when disabled.
The Support and Interface Logic use 6 clocks: -
• SysClock: Non-gated 13.824MHz clock.
• SysClock1: Clock to the 8032Turbo.This clock is inverted relative to the other four SysClocks. Enabled for (clocks_unstable=0).
• SysClock2: Clock to the Processor-Writeable registers. Controlled by the Processor Interface.
• SysClock3: Clock to the Speech Interface Logic (which is not needed by the CODEC). Controlled by Processor-writeable
register.
• SysClock4: Clock to the Ringer Tone Generator. Controlled by Processor-writeable register.
• SysClock5:Clock to the Winbond Linear CODEC (and logic in the Speech Interface needed to support operation of the CODEC)
Care will be required in the physical design of the Support Logic to ensure balancing of all clocks.
All outputs from logic in the 32768Hz clock domain are re-timed on entering the 13.824MHz clock domain. This is done using serial
pairs of latches to give metastability protection.
Signals in Interface Logic are re-timed: -
• KeyPress interrupt
• WatchDog interrupt
• WatchDog kick
• 1 millisecond timer interrupt
• 1 second timer interrupt
8.1.3
Clock Enable Register
Address
0x1440
Access Mode Value At Reset Nominal Value
R/W
0xFD
Bit 7
Reset32K
Sysclock3En
Bit 6
Bit 5
Bit 4
Blocked (for test modes)
When set, enable system clock 3.
Bit 3
Bit 2
Bit 1
Bit 0
SysClock5En SysClock4En SysClock3En
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Publication Release Date: May, 2007
Revision 1.3