W681307 Datasheet, PDF(7/160 Page) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

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W681307 Datasheet, PDF (7/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

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W681307

14.2 ADC Adaptive Bit Flip Probability................................................................................. - 110 -

14.3 Sounder Signal Selection ................................................................................................ - 111 -

14.4 Frequency Adjustment of Crystal Oscillator................................................................... - 112 -

14.5 Specific Register ............................................................................................................. - 113 -

14.6 VAG Selection................................................................................................................ - 113 -

14.7 TG Gain Register............................................................................................................ - 114 -

14.8 PO Gain Register............................................................................................................ - 115 -

14.9 The PCM CODEC .......................................................................................................... - 117 -

14.9.1

Block Diagram ........................................................................................................... - 117 -

14.9.2

Analog Interface and Signal Path............................................................................... - 117 -

14.9.3

Control Register: CODEC_CTRL ............................................................................... - 118 -

14.9.4

Specific Register......................................................................................................... - 119 -

14.9.5

Specific Register......................................................................................................... - 119 -

14.10 RECEIVE_DIAG............................................................................................................. - 119 -

14.11 Specific Register ............................................................................................................. - 121 -

14.12 EnAllClock..................................................................................................................... - 121 -

14.13 CODEC_Test_Sel ........................................................................................................... - 121 -

14.14 Test_SYSCLKOUT.......................................................................................................... - 122 -

14.15 BGP_LPF_EN................................................................................................................. - 122 -

14.16 CODEC Status Indicator................................................................................................. - 122 -

14.17 BandGap Voltage Adjustment........................................................................................ - 123 -

14.18 Specific Register ............................................................................................................. - 123 -

14.19 Linear Regulator Voltage Controller Register................................................................. - 123 -

14.20 Core PWR_Det ............................................................................................................... - 124 -

14.21 DA High Pass Filter Selection......................................................................................... - 124 -

14.22 TI Path Selection............................................................................................................. - 125 -

15. SERIAL PERIPHERAL INTERFACE................................................................................... - 127 -

15.1 Serial Peripheral Interface â SPI signals.......................................................................... - 127 -

15.1.1

SPI_Control 0............................................................................................................. - 128 -

15.1.2

SPI_Control 1............................................................................................................. - 128 -

15.1.3

SPI Status................................................................................................................... - 129 -

15.1.4

SPI Interrupt Enable .................................................................................................. - 129 -

15.1.5

DumpByte ................................................................................................................. - 129 -

15.1.6

Write TX FIFO ........................................................................................................... - 129 -

15.1.7

Read RX FIFO ............................................................................................................ - 130 -

15.1.8

SPI_Transfer_Size ...................................................................................................... - 130 -

15.1.9

SPI_Start_rtx.............................................................................................................. - 130 -

16. SPI FOR SERIAL DATA FLASH ......................................................................................... - 131 -

16.1 Introduction to SPI of Serial Data Flash .......................................................................... - 131 -

16.2 Block Diagram ............................................................................................................... - 131 -

16.3 Data Format ................................................................................................................... - 132 -

16.4 FSM................................................................................................................................ - 134 -

16.5 FIFO/RAM .................................................................................................................... - 134 -

16.6 Interrupt ........................................................................................................................ - 134 -

16.7 DF_SPI Register Group .................................................................................................. - 134 -

16.7.1

DF_CLK..................................................................................................................... - 134 -

16.7.2

DF_CMD_LEN .......................................................................................................... - 135 -

16.7.3

DF_DATA_LEN ........................................................................................................ - 135 -

-7-

Publication Release Date: May, 2007

Revision 1.3

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