W681307 Datasheet, PDF (64/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
10.7.2.4
Address
0x1703h
RX delay1
Access Mode
R/W
Value At Reset
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX delay1
Set the values for delaying the received bits of PCM B1 channel after the rising edge of the Fsync. The resolution is one Bitclk in full
date rate and two Bitclk in half data rate.
10.7.2.5
Address
0x1704h
RX delay2
Access Mode
R/W
Value At Reset
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX delay2
Set the values for delaying the received bits of PCM B2 channel after the tail bit of Rx PCM Highway B1 channel. The resolution is one
Bitclk in full date rate and two Bitclk in half data rate.
10.7.2.6
Address
0x1708h
PCM channel format and delay control of 2nd group (PCM B3, PCM B4)
Access Mode
R/W
Value At Reset
0x02
Bit 7
Bit 6
Bit 5
Bit 4
PCMB3_dis Half rate PCMB4_dis RESERVED
Bit 3
Hizen
Half/Full
Bit 2
RESERVED
Bit 1
Data
16/8bits
Bit 0
RESERVED
Data 16/8bits
Hizen Half/Full
PCMB4_dis
Half rate
PCMB3_dis
Set the bit to receive/transmit 16 bits; Reset the bit to receive/transmit 8 bits.
Set the bit to tristate in the end of the bit. Reset the bit to tristate in the falling edge of the end of the
bit.
=1: disabling the B4 channel of the PCM Highway.
=0: enabling the B4 channel of the PCM Highway.
Set the bit for one bit per 2 Bitclk (during data length being 16 bits=>0x1708 [1] =1’b1). Reset the bit
for one bit per 1 Bitclk.
=1: disabling the B3 channel of the PCM Highway.
=0: enabling the B3 channel of the PCM Highway.
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Publication Release Date: May, 2007
Revision 1.3