W681307 Datasheet, PDF (143/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
17.2.5
RdWrFIFO
Address
0x1744
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8-bit data from/to FIFO
This register can be used for W2S both read and write W2S-bus compatible device.
Writing data (including target device ID, high address, low address, and repeat ID, Data) to this register will be automatically stored in
W2S controller FIFO. When micro-C receives interrupt from W2S, micro-C need to check W2SStatus (0x1746) register to confirm the
※transmission is OK. If there is no error during W2S read process, micro-C can start reading FIFO content by reading RdWrFIFO register.
Micro-C must set RDActive bit (0x1745[5]) before start reading RdWrFIFO (0x1744) W2S FIFO content.
17.2.6
Force_Activity
Address
0x1745
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Bit 6
RESERVED RESERVED
Bit 5
RDActive
Bit 4
RESERVED
Bit 3
Rst_Rd_Ptr
Bit 2
Rst_Wr_Ptr
Bit 1
RDWRn
Bit 0
RDWR_en
RDActive: Set RDActive bit will enable the read capability of RdWrFIFO (0x1744).
To achieve STOP pattern on W2S bus at power on initial, it can send “acknowledge polling” pattern.
How to send “acknowledge polling” pattern:
After bit W2S_ENA (of register 1470) set 1, writes 0x00H or 0xA0H to FIFO (0x1744H). Finally, sets Force_Activity (0x1745) to 0x01H.
After these operations, W2C controller can start reading from or writing to EEPROM. This mechanism used for once when power on is
an option to enhance EEPROM stability.
Set Rst_Rd_Ptr bit will rest W2S controller internal FIFO read pointer.
Set Rst_Wr_Ptr bit will rest W2S controller internal FIFO write pointer.
RDWRn: For Read operation, reset RDWRn to 0, for Write operation, set RDWRn to 1.
Set RDWR_en bit will enable read or write operation depend on RDWRn.
※ Micro-C must set W2S_ENA bit before setup Force_Activity.
※ Write 0xFF to 0x1746 to reset all W2S_Status bits and reset W2S-FIFO both read and write pointer (0x1745[3] and 0x1745[2] set to 1)
and then clear (0x1745[3] and 0x1745[2] reset to 0) before enable read or write operation.
17.2.7
W2S_Status
Address
0x1746
Access Mode Value At Reset Nominal Value
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED RESERVED RESERVED RESERVED RESERVED FIFO_empty
Bit 1
FIFO_full
Bit 0
ACK_Fail
FIFO_empty bit will generate W2S interrupt during write operation.
FIFO_full bit will generate W2S interrupt during read operation.
ACK_Fail bit indicates that there is no response for target device during ACK period Rread or Write process, this bit will generate W2S
※interrupt.
W2S_Status register content is valid only if W2S_ENA bit has been set.
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Publication Release Date: May, 2007
Revision 1.3