W681307 Datasheet, PDF (135/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM

W681307
DF_ENB
16.7.2
When set, enable DF_SPI module.
When reset, disable DF_SPI module.
Note: The FIFO/RAM only can be access while this bit is set enable.
DF_CMD_LEN
Address
0x1731
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
CMD_LEN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DATA_ENB DF_RD
CMD_LEN [2:0]
≦ Command Field Length. (unit: byte,CMD_LEN 4 )
Command Field Length = CMD_LEN + 1
EX: CMD_LEN = 0x03 → Command Field Length = 4 bytes.
DF_RD
Read/Write Flag. (1: Read,0: Write)
DATA_ENB
Enable Data Field. (1: Enable, 0: Disable)
Note: While DF_ENB = 1, write this byte will force DF module start to TX/RX
16.7.3
DF_DATA_LEN
Address
0x1732
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
Bit 6
DATA_LEN
Bit 5
Bit 4
Bit 3
Bit 2
DATA_LEN [7:0]
Data Field Length.(unit: byte)
Data Field Length = DATA_LEN + 1
EX: DATA_LEN = 0x0F → Data Field Length = 16 bytes.
Bit 1
Bit 0
16.7.4
DF_INTR_REG
Address
0x1733
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
INTR_ENB
TX_OK
Bit 6
Bit 5
INTR_CNT [3:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD_FLAG RX_OK TX_OK INTR_ENB
When set, enable DF module interrupt.
When reset, disable DF module interrupt.
This module support 2 kind of interrupt source. One is the TX/RX Finished interrupt
(occurred while TX/RX bytes = DATA_LEN), the other is internal pre-interrupt (occurred
while TX/RX bytes = INTR_CNT * 16).
TX Finish Interrupt.( Read Only)
This bit will be clear automatically while next TX/RX
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Publication Release Date: May, 2007
Revision 1.3