W972GG6JB-18-TR Datasheet, PDF (74/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM

W972GG6JB
11.10 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4)
T0
CLK
CLK
CMD
Post CAS
READ A
T1
NOP
T2
T3
Post CAS
READ B
NOP
T4
NOP
T5
NOP
T6
NOP
T7
NOP
T8
NOP
DQS
DQS
DQ's
AL = 2
RL = 5
CL = 3
DOUT DOUT DOUT DOUT DOUT DOUT DOUT
A0
A1
A2
A3
B0
B1
B2
Note:
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and
every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are
activated.
11.11 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4)
T0
CLK
CLK
CMD ^{Post CAS}
Write A
T1
NOP
T2
T3
Post CAS
Write B
NOP
T4
NOP
T5
NOP
T6
NOP
T7
NOP
T8
NOP
DQS
DQS
DQ's
WL = RL - 1 = 4
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
A0
A1
A2
A3
B0
B1
B2
B3
Note:
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four
clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
- 74 -
Publication Release Date: Jul. 28, 2014
Revision: A03