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| W972GG6JB-18-TR Datasheet, PDF (58/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM | |||
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W972GG6JB
CLK
CLK
VDDQ
tIS
tIH
VIH(ac)min
VIH(dc)min
DC to VREF
region
VREF(dc)
VIL(dc)max
nominal
slew rate
VIL(ac)max
tIS
tIH
nominal
slew rate
DC to VREF
region
VSS
ÎTR
ÎTF
Hold Slew Rate VREF(dc) - VIL(dc)max
Rising Signal =
ÎTR
Hold Slew Rate VIH(dc)min - VREF(dc)
Falling Signal =
ÎTF
Figure 22 â Illustration of nominal slew rate for tIH
- 58 -
Publication Release Date: Jul. 28, 2014
Revision: A03
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