W972GG6JB-18-TR Datasheet, PDF (31/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM

W972GG6JB
9. OPERATION MODE
9.1 Command Truth Table
COMMAND
Bank Activate
Single Bank
Precharge
Precharge All
Banks
Write
Write with
Auto-precharge
Read
Read with
Auto-precharge
(Extended)
Mode Register
Set
CKE
Previous Current
Cycle
Cycle
H
H
BA2
BA1
BA0
BA
H
H
BA
H
H
X
H
H
BA
H
H
BA
H
H
BA
H
H
BA
H
H
BA
A13
A12
A10 A9-A0
A11
Row Address
X
L
X
X
H
X
Column L Column
Column H Column
Column L Column
Column H Column
OP Code
CS RAS CAS WE
L
L
H
H
L
L
H
L
L
L
H
L
L
H
L
L
L
H
L
L
L
H
L
H
L
H
L
H
L
L
L
L
NOTES
1,2
1,2
1
1,2,3
1,2,3
1,2,3
1,2,3
1,2
No Operation
H
X
X
X
X
X
L
H
H
H
1
Device
Deselect
H
Refresh
H
Self Refresh
Entry
H
Self Refresh
Exit
L
Power Down
Mode Entry
H
X
X
X
X
X
H
X
X
X
1
H
X
X
X
X
L
L
L
H
1
L
X
X
X
X
L
L
L
H
1,4
H
X
X
X
H
X
X
X
X
1,4,5
L
H
H
H
H
X
X
X
L
X
X
X
X
1,6
L
H
H
H
Power Down
Mode Exit
L
H
X
X
X
H
X
X
X
X
1,6
L
H
H
H
Notes:
1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA [2:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See “Burst Interrupt” in section 8.5 for details.
4. V_REF must be maintained during Self Refresh operation.
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 8.9.
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Publication Release Date: Jul. 28, 2014
Revision: A03