W972GG6JB-18-TR Datasheet, PDF (7/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM

W972GG6JB
6. BALL DESCRIPTION
BALL NUMBER SYMBOL
FUNCTION
DESCRIPTION
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2,R8
A0−A13
Address
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
Row address: A0−A13.
Column address: A0−A9. (A10 is used for Auto-precharge)
L2,L3,L1
BA0−BA2
Bank Select
BA0−BA2 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
G8,G2,H7,H3,H1,H9
,F1,F9,C8,C2,D7,D3, DQ0−DQ15
D1,D9,B1,B9
Data Input
/ Output
Bi-directional data bus.
K9
ODT
On Die Termination ODT (registered HIGH) enables termination resistance internal to the
Control
DDR2 SDRAM.
F7,E8
LDQS, LDQS
LOW Data Strobe
Data Strobe for Lower Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. LDQS corresponds to the data on
DQ0−DQ7. LDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
B7,A8
UDQS, UDQS ^{UP Data Strobe}
Data Strobe for Upper Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. UDQS corresponds to the data on
DQ8−DQ15. UDQS is only used when differential data strobe
mode is enabled via the control bit at EMR (1)[A10 EMRS command].
All commands are masked when CS is registered HIGH. CS
L8
CS
Chip Select
provides for external rank selection on systems with multiple ranks.
CS is considered part of the command code.
K7,L7,K3
B3,F3
RAS , CAS ,
WE
UDM, LDM
Command Inputs
Input Data Mask
RAS , CAS and WE (along with CS ) define the command being
entered.
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
J8,K8
CLK, CLK
K2
J2
A1,E1,J9,M9,R1
A3,E3,J3,N1,P9
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
A2,E2,R3,R7
J7
J1
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
VSSDL
VDDL
Differential Clock
Inputs
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
Clock Enable
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
Reference Voltage VREF is reference voltage for inputs.
Power Supply Power Supply: 1.8V ± 0.1V.
Ground
Ground.
DQ Power Supply DQ Power Supply: 1.8V ± 0.1V.
DQ Ground
DQ Ground. Isolated on the device for improved noise immunity.
No Connection No connection.
DLL Ground
DLL Ground.
DLL Power Supply DLL Power Supply: 1.8V ± 0.1V.
Publication Release Date: Jul. 28, 2014
Revision: A03
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