W972GG6JB-18-TR Datasheet, PDF (45/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM

W972GG6JB
10.11.2 AC Characteristics and Operating Condition for -25/25I/-3/-3I speed grade
Notes: 1-3 and 45-47 apply to the entire table
SPEED GRADE
SYM.
Bin(CL-tRCD-tRP)
PARAMETER
tRCD Active to Read/Write Command Delay Time
tRP Precharge to Active Command Period
tRC Active to Ref/Active Command Period
tRAS Active to Precharge Command Period
tRFC
Auto Refresh to Active/Auto Refresh command
period
tREFI
Average periodic
refresh Interval
-40°C ≤ TCASE ≤ 85°C*
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
DDR2-800
(-25/25I)
5-5-5/6-6-6
MIN.
MAX.
12.5

12.5

57.5

45
70000
195


7.8*

7.8

3.9
DDR2-667
(-3/-3I)
5-5-5
MIN. MAX.
15

15

60

45
70000
UNITS²⁵ NOTES
nS
23
nS
23
nS
23
nS
4,23
195

nS
5

7.8*
μS
5

7.8
μS
5

3.9
μS
5,6
tCCD _{CAS to CAS command delay}
tCK(avg) @ CL=3
tCK(avg) Average clock period
tCK(avg) @ CL=4
tCK(avg) @ CL=5
tCK(avg) @ CL=6
tCH(avg) Average clock high pulse width
tCL(avg) Average clock low pulse width
tAC _{DQ output access time from CLK/ CLK}
2
5
3.75
2.5
2.5
0.48
0.48
-400

2

nCK
8
5
8
nS
30,31
8
3.75
8
nS
30,31
8
3
8
nS
30,31
8


nS
30,31
0.52
0.48
0.52 tCK(avg) 30,31
0.52
0.48
0.52 tCK(avg) 30,31
400
-450
450
pS
35
tDQSCK _{DQS output access time from CLK / CLK}
tDQSQ DQS-DQ skew for DQS & associated DQ signals
tCKE CKE minimum high and low pulse width
tRRD Active to active command period for 2KB page size
tFAW Four Activate Window for 2KB page size
tWR Write recovery time
tDAL Auto-precharge write recovery + precharge time
tWTR Internal Write to Read command delay
tRTP Internal Read to Precharge command delay
-350

3
10
45
15
WR + tnRP
7.5
7.5
tIS (base) Address and control input setup time
175
350
-400
400
200

240

3


10


50


15

 WR + tnRP 

7.5


7.5


200

tIH (base) Address and control input hold time
250

275

tIS (ref) Address and control input setup time
375

400

tIH (ref) Address and control input hold time
tIPW Address and control input pulse width for each input
tDQSS
DQS latching rising transitions to associated clock
edges
tDSS DQS falling edge to CLK setup time
tDSH DQS falling edge hold time from CLK
tDQSH DQS input high pulse width
tDQSL DQS input low pulse width
* -40°C ≤ TCASE ≤ 85°C is for 25I/-3I grade only.
375
0.6
-0.25
0.2
0.2
0.35
0.35

400


0.6

0.25
-0.25
0.25

0.2


0.2


0.35


0.35

pS
35
pS
13
nCK
7
nS
8,23
nS
23
nS
23
nCK
24
nS
9,23
nS
4,23
pS
10,26,
40,42,43
pS
11,26,
40,42,43
pS
10,26,
40,42,43
pS
11,26,
40,42,43
tCK(avg)
tCK(avg)
28
tCK(avg)
28
tCK(avg)
28
tCK(avg)
tCK(avg)
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Publication Release Date: Jul. 28, 2014
Revision: A03