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| W972GG6JB-18-TR Datasheet, PDF (56/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM | |||
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W972GG6JB
CLK
CLK
VDDQ
tIS tIH
VIH(ac)min
VREF to AC
region
VIH(dc)min
VREF(dc)
VIL(dc)max
nominal
slew rate
VIL(ac)max
tIS
tIH
nominal
slew rate
VREF to AC
region
VSS
ÎTF
Setup Slew Rate
Falling Signal
=
VREF(dc) - VIL(ac)max
ÎTF
ÎTR
Setup Slew Rate
VIH(ac)min - VREF(dc)
Rising Signal =
ÎTR
Figure 20 â Illustration of nominal slew rate for tIS
- 56 -
Publication Release Date: Jul. 28, 2014
Revision: A03
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