W972GG6JB-18-TR Datasheet, PDF (35/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM

W972GG6JB
Function Truth Table, continued
CURRENT
STATE
Write
Recovering
CS RAS CAS WE ^{ADDRESS COMMAND}
H
X
X
X
X
DSL
L
H
H
H
X
NOP
L
H
L
H BA, CA, A10 READ/READA
L
H
L
L BA, CA, A10 WRIT/WRITA
L
L
H
H BA, RA
ACT
L
L
H
L BA, A10
PRE/PREA
L
L
L
H
X
REF/SELF
L
L
L
L Op-Code
MRS/EMRS
ACTION
NOP-> Bank active after tWR
NOP-> Bank active after tWR
ILLEGAL
New write
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOTES
1
1
1
H
X
X
X
X
DSL
NOP-> Precharge after tWR
L
H
H
H
X
NOP
NOP-> Precharge after tWR
L
H
L
H BA, CA, A10 READ/READA
ILLEGAL
1
Write
Recovering ^L
H
L
L BA, CA, A10 WRIT/WRITA
ILLEGAL
1
with Auto-
L
L
H
H BA, RA
precharge
ACT
ILLEGAL
1
L
L
H
L BA, A10
PRE/PREA
ILLEGAL
1
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP-> Idle after tRC
L
H
H
H
X
NOP
NOP-> Idle after tRC
L
H
L
H BA, CA, A10 READ/READA
ILLEGAL
L
H
L
L BA, CA, A10 WRIT/WRITA
Refreshing
L
L
H
H BA, RA
ACT
ILLEGAL
ILLEGAL
L
L
H
L BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L Op-Code
MRS/EMRS
ILLEGAL
H
X
X
X
X
DSL
NOP-> Idle after tMRD
L
H
H
H
X
NOP
NOP-> Idle after tMRD
L
H
L
H BA, CA, A10 READ/READA
ILLEGAL
Mode
L
H
L
L BA, CA, A10 WRIT/WRITA
Register
Accessing ^L
L
H
H BA, RA
ACT
ILLEGAL
ILLEGAL
L
L
H
L BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L Op-Code
MRS/EMRS
ILLEGAL
Notes:
1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in “IDLE”.
3. Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8. Burst read/write can
only be interrupted by another read/write with 4 bit burst boundary. Any other case of read/write interrupt is not allowed.
Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data.
- 35 -
Publication Release Date: Jul. 28, 2014
Revision: A03