W972GG6JB-18-TR Datasheet, PDF (51/87 Pages) Winbond – 16M 8 BANKS 16 BIT DDR2 SDRAM

W972GG6JB
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
PARAMETER
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period
Cycle to cycle clock period jitter during DLL
locking period
SYMBOL
tJIT(per)
tJIT(per,lck)
tJIT(cc)
tJIT(cc,lck)
DDR2-667
MIN. MAX.
-125 125
-100 100
-250 250
-200 200
DDR2-800
MIN. MAX.
-100 100
-80
80
-200 200
-160 160
DDR2-1066
MIN. MAX.
-90
90
-80
80
-180 180
-160 160
UNIT
pS
pS
pS
pS
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles,
n = 6 ... 10, inclusive
Cumulative error across n cycles,
n = 11 ... 50, inclusive
Duty cycle jitter
tERR(2per)
-175 175 -150 150 -132 132 pS
tERR(3per)
-225 225 -175 175 -157 157 pS
tERR(4per)
-250 250 -200 200 -175 175 pS
tERR(5per)
-250 250 -200 200 -188 188 pS
tERR(6-10per) -350 350 -300 300 -250 250 pS
tERR(11-50per) -450 450 -450 450 -425 425 pS
tJIT(duty)
-125 125 -100 100 -75
75
pS
Definitions:
- tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
^N

 ^{tCK(avg) =}  ^tCK j  ^{/ N}
 ^{j 1}

where N = 200
- tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
^{ N}

tCH(avg) = _ tCH _{j } / (N × tCK(avg))
 ^{j 1}

where N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
^{ N}

tCL(avg) = _ tCL _{j } / (N × tCK(avg))
 ^{j 1}

where N = 200
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Publication Release Date: Jul. 28, 2014
Revision: A03