W981216AH Datasheet, PDF (6/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
2M x 16 bit x 4 Banks SDRAM
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc=3.3V±0.3V, Ta=0° to 70°C Notes:5, 6, 7, 8)
SYMBOL
PARAMETER
tRC
Ref/Active to Ref/Active Command Period
tRAS
Active to precharge Command Period
tRCD
Active to Read/Write Command Delay Time
tCCD
Read/Write(a) to Read/Write(b)Command Period
tRP
Precharge to Active Command Period
tRRD
Active(a) to Active(b) Command Period
tWR
Write Recovery Time
tCK
CLK Cycle Time
tCH
CLK High Level width
tCL
CLK Low Level width
tAC
Access Time from CLK
tOH
Output Data Hold Time
tHZ
Output Data High Impedance Time
tLZ
Output Data Low Impedance Time
tSB
Power Down Mode Entry Time
tT
Transition Time of CLK (Rise and Fall)
tDS
Data-in Set-up Time
tDH
Data-in Hold Time
tAS
Address Set-up Time
tAH
Address Hold Time
tCKS
CKE Set-up Time
tCKH
CKE Hold Time
tCMS
Command Set-up Time
tCMH
Command Hold Time
tREF
Refresh Time
tRSC
Mode register Set Cycle Time
CL*=2
CL*=3
CL*=2
CL*=3
CL*=2
CL*=3
-75 (PC133)
MIN
MAX
65
45 100000
20
1
20
15
10
7.5
10
1000
7.5
1000
2.5
2.5
6
5.4
2.7
2.7
7.5
0
0
7.5
0.5
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
15
-8H (PC100)
MIN
MAX
68
48 100000
20
1
20
20
10
8
10
1000
8
1000
3
3
6
6
3
3
8
0
0
8
0.5
10
2
1
2
1
2
1
2
1
64
16
UNIT
ns
cycle
ns
ms
ns
(CL=CAS Latency)
Revision 1.0
Publication Release Date: March, 1999
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