W981216AH Datasheet, PDF (40/44 Pages) Winbond – 2M x 16 bit x 4 Banks SDRAM

W981216AH
2M x 16 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Precharge Command )
In the case of Burst Lenght = 8
0
1
2
3
4
5
6
7
8
9
(1) Read cycle
( a )CAS latency =2
Commad
Read
PRCG
DQ
( b )CAS latency = 3
Commad
Read
Q0 Q1 Q2 Q3 Q4
PRCG
DQ
( c )CAS latency = 4
Commad
Read
Q0 Q1 Q2 Q3 Q4
PRCG
DQ
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
( a ) CAS latency =2
Commad
DQM
Write
PRCG
tWR
DQ _{D0 D1 D2 D3 D4}
( b )CAS latency = 3
Commad
Write
PRCG
tWR
DQM
DQ _{D0 D1 D2 D3} D4
( c )CAS latency = 4
Commad
Write
PRCG
tWR
DQM
DQ _{D0 D1 D2 D3 D4}
10 11
Note )
PRCG represents the Precharge command
Revision 1.0
- 40 -
Publication Release Date: March, 1999